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» On Modeling Cross-Talk Faults
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DATE
2000
IEEE
136views Hardware» more  DATE 2000»
14 years 1 months ago
Parametric Fault Simulation and Test Vector Generation
Process variation has forever been the major fail cause of analog circuit where small deviations in component values cause large deviations in the measured output parameters. This...
Khaled Saab, Naim Ben Hamida, Bozena Kaminska
FMSP
2000
ACM
152views Formal Methods» more  FMSP 2000»
14 years 1 months ago
Fault origin adjudication
When a program P fails to satisfy a requirement R supposedly ensured by a detailed speci cation S that was used to implement P, there is a question about whether the problem arise...
Karthikeyan Bhargavan, Carl A. Gunter, Davor Obrad...
DATE
1999
IEEE
144views Hardware» more  DATE 1999»
14 years 1 months ago
A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester
This work presents a new diagnosis method for use in an adaptive analog tester. The tester is able to detect faults in any linear circuit by learning a reference behavior in a fir...
Érika F. Cota, Luigi Carro, Marcelo Lubasze...
DATE
1999
IEEE
111views Hardware» more  DATE 1999»
14 years 1 months ago
Sequential Circuit Test Generation Using Decision Diagram Models
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...
Jaan Raik, Raimund Ubar
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
14 years 3 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...