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» On Modeling Cross-Talk Faults
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ATS
2003
IEEE
87views Hardware» more  ATS 2003»
14 years 1 months ago
March SL: A Test For All Static Linked Memory Faults
The analysis of linked faults has proven to be a source for new memory tests, characterized by an increased fault coverage. The paper gives a set of five new tests to target all ...
Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mik...
JCO
2008
85views more  JCO 2008»
13 years 8 months ago
Locating and detecting arrays for interaction faults
The identification of interaction faults in component-based systems has focussed on indicating the presence of faults, rather than their location and magnitude. While this is a va...
Charles J. Colbourn, Daniel W. McClary
HPCA
2009
IEEE
14 years 9 months ago
Accurate microarchitecture-level fault modeling for studying hardware faults
Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault t...
Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu...
DFT
2002
IEEE
127views VLSI» more  DFT 2002»
14 years 1 months ago
A New Functional Fault Model for FPGA Application-Oriented Testing
1 The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates t...
Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo ...
IPPS
2002
IEEE
14 years 1 months ago
A Limited-Global Fault Information Model for Dynamic Routing in 2-D Meshes
In this paper, a fault-tolerant routing in 2-D meshes with dynamic faults is provided. It is based on an early work on minimal routing in 2-D meshes with static faults. Unlike man...
Zhen Jiang, Jie Wu