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» On Optimal Tolerancing in Computer-Aided Design
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CODES
2005
IEEE
14 years 1 months ago
Key research problems in NoC design: a holistic perspective
Networks-on-Chip (NoCs) have been recently proposed as a promising solution to complex on-chip communication problems. The lack of an unified representation of applications and ar...
Ümit Y. Ogras, Jingcao Hu, Radu Marculescu
SMA
2010
ACM
171views Solid Modeling» more  SMA 2010»
13 years 7 months ago
Efficient simplex computation for fixture layout design
Designing a fixture layout of an object can be reduced to computing the largest simplex and the resulting simplex is classified using the radius of the largest inscribed ball cent...
Yu Zheng, Ming C. Lin, Dinesh Manocha
GECCO
2007
Springer
198views Optimization» more  GECCO 2007»
14 years 1 months ago
On the design of optimisers for surface reconstruction
In many industrial applications the need for an efficient and high-quality reconstruction of free-form surfaces does exist. Surface Reconstruction – the generation of CAD models...
Tobias Wagner, Thomas Michelitsch, Alexei Sacharow
VLSID
2009
IEEE
99views VLSI» more  VLSID 2009»
14 years 8 months ago
Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips
In this paper, we present a dynamic power management technique for optimizing the use of virtual channels in network on chips. The technique which is called dynamic virtual channe...
Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afz...
ICCAD
2004
IEEE
114views Hardware» more  ICCAD 2004»
14 years 4 months ago
Simultaneous short-path and long-path timing optimization for FPGAs
This paper presents the Routing Cost Valleys (RCV) algorithm – the first published algorithm that simultaneously optimizes all short- and long-path timing constraints in a Field...
Ryan Fung, Vaughn Betz, William Chow