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» On Optimization of Test Parallelization with Constraints
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ASPDAC
2007
ACM
119views Hardware» more  ASPDAC 2007»
14 years 1 months ago
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng,...
CLUSTER
2007
IEEE
14 years 29 days ago
A feasibility analysis of power-awareness and energy minimization in modern interconnects for high-performance computing
High-performance computing (HPC) systems consume a significant amount of power, resulting in high operational costs, reduced reliability, and wasting of natural resources. Therefor...
Reza Zamani, Ahmad Afsahi, Ying Qian, V. Carl Hama...
CCGRID
2008
IEEE
13 years 11 months ago
Scheduling of Scientific Workflows on Data Grids
Selection of resources for execution of scientific workflows in data grids becomes challenging with the exponential growth of files as a result of the distribution of scientific e...
Suraj Pandey, Rajkumar Buyya
IAT
2008
IEEE
14 years 3 months ago
Competency-Based Intelligent Curriculum Sequencing: Comparing Two Evolutionary Approaches
The process of creating e-learning contents using reusable learning objects (LOs) can be broken down in two sub-processes: LOs finding and LO sequencing. Although semiautomatic to...
Luis de Marcos, Roberto Barchino, José-Javi...
MP
2007
97views more  MP 2007»
13 years 8 months ago
On the domino-parity inequalities for the STSP
Abstract One method which has been used very successfully for finding optimal and provably good solutions for large instances of the Symmetric Travelling Salesman Problem (STSP) i...
Sylvia C. Boyd, Sally Cockburn, Danielle Vella