867 search results - page 7 / 174 » On Optimization of Test Parallelization with Constraints |
TCAD
2002
13 years 7 months ago
2002
Test scheduling is an important problem in system-on-a-chip (SOC) test automation. Efficient test schedules minimize the overall system test application time, avoid test resource c...
IPPS
1997
IEEE
13 years 11 months ago
1997
IEEE
Naive parallel implementation of nondeterministic systems (such as a theorem proving system) and languages (such as a logic, constraint, or a concurrent constraint language)can re...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. ...
ICASSP
2011
IEEE
12 years 11 months ago
2011
IEEE
In this paper, we propose a new methodology for detecting lane markers that exploits the parallel nature of lane boundaries on the road. First, the input image is pre-processed an...
SIGSOFT
2007
ACM
14 years 8 months ago
2007
ACM
We present novel algorithms for parallel testing of code that takes structurally complex test inputs. The algorithms build on the Korat algorithm for constraint-based generation o...