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» On Packing Densities of Permutations
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ASPDAC
2009
ACM
104views Hardware» more  ASPDAC 2009»
14 years 2 months ago
Addressing thermal and power delivery bottlenecks in 3D circuits
— The enhanced packing densities facilitated by 3D integrated circuit technology also has an unwanted side-effect, in the form of increasing the amount of current per unit footpr...
Sachin S. Sapatnekar
VLSISP
2008
173views more  VLSISP 2008»
13 years 7 months ago
Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors
Advanced bit manipulation operations are not efficiently supported by commodity word-oriented microprocessors. Programming tricks are typically devised to shorten the long sequence...
Yedidya Hilewitz, Ruby B. Lee
GLOBECOM
2006
IEEE
14 years 1 months ago
Investigation of Error Floors of Structured Low-Density Parity-Check Codes by Hardware Emulation
Abstract−Several high performance LDPC codes have paritycheck matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any str...
Zhengya Zhang, Lara Dolecek, Borivoje Nikolic, Ven...
CORR
2008
Springer
106views Education» more  CORR 2008»
13 years 7 months ago
Construction of Near-Optimum Burst Erasure Correcting Low-Density Parity-Check Codes
In this paper, a simple and effective tool for the design of low-density parity-check (LDPC) codes for iterative correction of bursts of erasures is presented. The design method co...
Enrico Paolini, Marco Chiani
SAMOS
2004
Springer
14 years 24 days ago
Scalable Instruction-Level Parallelism.
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
Chris R. Jesshope