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DATE
1999
IEEE
162views Hardware» more  DATE 1999»
14 years 2 months ago
MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
Robert P. Dick, Niraj K. Jha
ITC
1999
IEEE
107views Hardware» more  ITC 1999»
14 years 2 months ago
A high-level BIST synthesis method based on a region-wise heuristic for an integer linear programming
A high-level built-in self-test (BIST) synthesis involves several tasks such as system register assignment, interconnection assignment, and BIST register assignment. Existing high...
Han Bin Kim, Dong Sam Ha
SPAA
1998
ACM
14 years 2 months ago
Elimination Forest Guided 2D Sparse LU Factorization
Sparse LU factorization with partial pivoting is important for many scienti c applications and delivering high performance for this problem is di cult on distributed memory machin...
Kai Shen, Xiangmin Jiao, Tao Yang
EUROPAR
1998
Springer
14 years 2 months ago
Parallel Sparse Matrix Computations Using the PINEAPL Library: A Performance Study
Abstract. The Numerical Algorithms Group Ltd is currently participating in the European HPCN Fourth Framework project on Parallel Industrial NumErical Applications and Portable Lib...
Arnold R. Krommer
SIGGRAPH
1994
ACM
14 years 1 months ago
IRIS performer: a high performance multiprocessing toolkit for real-time 3D graphics
This paper describes the design and implementation of IRIS Performer, a toolkit for visual simulation, virtual reality, and other real-time 3D graphics applications. The principal...
John Rohlf, James Helman