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» On Reducing Circuit Malfunctions Caused by Soft Errors
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ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes
- Two methods to apply tests to detect delay faults in standard scan designs are used. One is called launch off capture and the other is called launch off shift. Launch off shift t...
Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz
DATE
2005
IEEE
204views Hardware» more  DATE 2005»
14 years 1 months ago
Evaluation of Error-Resilience for Reliable Compression of Test Data
This paper addresses error-resilience as the capability to tolerate bit-flips in a compressed test data stream (which is transferred from an Automatic Test Equipment (ATE) to the...
Hamidreza Hashempour, Luca Schiano, Fabrizio Lomba...
MICRO
2006
IEEE
159views Hardware» more  MICRO 2006»
13 years 7 months ago
MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits
Shrinking devices to the nanoscale, increasing integration densities, and reducing of voltage levels down to the thermal limit, all conspire to produce faulty systems. Frequent oc...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
ICCAD
1992
IEEE
148views Hardware» more  ICCAD 1992»
13 years 11 months ago
McPOWER: a Monte Carlo approach to power estimation
Excessive power dissipation in integrated circuits causes overheating and can lead to soft errors and or permanent damage. The severity of the problem increases in proportion to t...
Richard Burch, Farid N. Najm, Ping Yang, Timothy N...
DAC
2009
ACM
14 years 8 months ago
Improving testability and soft-error resilience through retiming
State elements are increasingly vulnerable to soft errors due to their decreasing size, and the fact that latched errors cannot be completely eliminated by electrical or timing ma...
Smita Krishnaswamy, Igor L. Markov, John P. Hayes