Sciweavers

2452 search results - page 448 / 491
» On Reduction of Lagrange Systems
Sort
View
HOTI
2008
IEEE
14 years 4 months ago
Network Processing on an SPE Core in Cell Broadband Engine
Cell Broadband EngineTM is a multi-core system on a chip and is composed of a general-purpose Power Processing Element (PPE) and eight Synergistic Processing Elements (SPEs). Its ...
Yuji Kawamura, Takeshi Yamazaki, Hiroshi Kyusojin,...
ICRA
2008
IEEE
136views Robotics» more  ICRA 2008»
14 years 4 months ago
Modeling multi-robot interaction using generalized occupancy grids, with application to reducing spatial interference
— As part of a program to find methods of reducing spatial interference in multi-robot systems, we propose the Interaction Grid (IG), a generalization of the Occupancy Grid that...
Mauricio Zuluaga, Richard T. Vaughan
IPPS
2007
IEEE
14 years 4 months ago
Load Miss Prediction - Exploiting Power Performance Trade-offs
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
Konrad Malkowski, Greg M. Link, Padma Raghavan, Ma...
MICRO
2007
IEEE
128views Hardware» more  MICRO 2007»
14 years 4 months ago
A Framework for Providing Quality of Service in Chip Multi-Processors
The trends in enterprise IT toward service-oriented computing, server consolidation, and virtual computing point to a future in which workloads are becoming increasingly diverse i...
Fei Guo, Yan Solihin, Li Zhao, Ravishankar Iyer
RSP
2007
IEEE
143views Control Systems» more  RSP 2007»
14 years 4 months ago
Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs
Multiprocessor Systems-on-Chip (MPSoCs) is a trend in VLSI design, since they minimize the “design crisis” (gap between silicon technology and actual SoC design capacity) and ...
Ewerson Carvalho, Ney Calazans, Fernando Moraes