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» On Reusing the Results of Pre-Executed Instructions in a Run...
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HPCA
2004
IEEE
14 years 9 months ago
Reducing Branch Misprediction Penalty via Selective Branch Recovery
Branch misprediction penalty consists of two components: the time wasted on mis-speculative execution until the mispredicted branch is resolved and the time to restart the pipelin...
Amit Gandhi, Haitham Akkary, Srikanth T. Srinivasa...
DAC
2006
ACM
13 years 10 months ago
Systematic software-based self-test for pipelined processors
Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving ...
Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis H...
ISCA
2000
IEEE
121views Hardware» more  ISCA 2000»
14 years 28 days ago
Selective, accurate, and timely self-invalidation using last-touch prediction
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...
An-Chow Lai, Babak Falsafi
ASAP
2007
IEEE
133views Hardware» more  ASAP 2007»
14 years 16 days ago
An Efficient Hardware Support for Control Data Validation
Software-based, fine-grain control flow integrity (CFI) validation technique has been proposed to enforce control flow integrity of program execution. By validating every indirect...
Yong-Joon Park, Zhao Zhang, Gyungho Lee