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» On Timing Analysis of Combinational Circuits
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ASPDAC
2005
ACM
131views Hardware» more  ASPDAC 2005»
13 years 10 months ago
Analysis of buffered hybrid structured clock networks
- This paper presents a novel approach for fast transient analysis of buffered hybrid structured clock networks. The new method applies structure reduction and relaxed hierarchical...
Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheld...
ICCAD
2001
IEEE
108views Hardware» more  ICCAD 2001»
14 years 5 months ago
Multigrid-Like Technique for Power Grid Analysis
— Modern sub-micron VLSI designs include huge power grids that are required to distribute large amounts of current, at increasingly lower voltages. The resulting voltage drop on ...
Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm
ISQED
2007
IEEE
254views Hardware» more  ISQED 2007»
14 years 2 months ago
An Aggregation-Based Algebraic Multigrid Method for Power Grid Analysis
ct This paper develops an aggregation-based algebraic multigrid (AbAMG) method to efficiently analyze the power grids. Different from the conventional algebraic multigrid (AMG) sc...
Pei-Yu Huang, Huan-Yu Chou, Yu-Min Lee
ISQED
2007
IEEE
148views Hardware» more  ISQED 2007»
14 years 2 months ago
On Accelerating Soft-Error Detection by Targeted Pattern Generation
Soft error due to ionizing radiation is emerging as a major concern for future technologies. The measurement unit for failures due to soft errors is called Failure-In-Time (FIT) t...
Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu
VTS
2003
IEEE
122views Hardware» more  VTS 2003»
14 years 1 months ago
A Reconfigurable Shared Scan-in Architecture
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) arc...
Samitha Samaranayake, Emil Gizdarski, Nodari Sitch...