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» On Timing Analysis of Combinational Circuits
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DATE
2008
IEEE
161views Hardware» more  DATE 2008»
14 years 2 months ago
Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression
Statistical timing analysis needs a priori knowledge of process variations. Lack of such a priori knowledge of process variations prevents accurate statistical timing analysis, fo...
Bao Liu
ECCC
2011
223views ECommerce» more  ECCC 2011»
13 years 3 months ago
A Case of Depth-3 Identity Testing, Sparse Factorization and Duality
Polynomial identity testing (PIT) problem is known to be challenging even for constant depth arithmetic circuits. In this work, we study the complexity of two special but natural ...
Chandan Saha, Ramprasad Saptharishi, Nitin Saxena
CODES
2002
IEEE
14 years 1 months ago
Worst-case performance analysis of parallel, communicating software processes
In this paper we present a method to perform static timing analysis of SystemC models, that describe parallel, communicating software processes.The paper combines a worstcase exec...
Axel Siebenborn, Oliver Bringmann, Wolfgang Rosens...
DATE
2008
IEEE
111views Hardware» more  DATE 2008»
14 years 2 months ago
Incremental Criticality and Yield Gradients
— Criticality and yield gradients are two crucial diagnostic metrics obtained from Statistical Static Timing Analysis (SSTA). They provide valuable information to guide timing op...
Jinjun Xiong, Vladimir Zolotov, Chandu Visweswaria...
ISQED
2010
IEEE
177views Hardware» more  ISQED 2010»
14 years 3 months ago
Multi-corner, energy-delay optimized, NBTI-aware flip-flop design
With the CMOS transistors being scaled to sub 45nm and lower, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging pr...
Hamed Abrishami, Safar Hatami, Massoud Pedram