Multi-corner, energy-delay optimized, NBTI-aware flip-flop design

With the CMOS transistors being scaled to sub 45nm and lower, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the corresponding reduction in the long-term reliability of CMOS circuits. This paper investigates the effect of NBTI phenomenon on the setup and hold times of flip-flops. First, it is shown that NBTI tightens the setup and hold timing constraints imposed on the flip-flops in the design. Second, an efficient algorithm is introduced for characterizing the codependent setup and hold time (CSHT) contours. Third, we introduce a multicorner optimization problem to minimize the energy-delay product of the flip-flops. The optimization relies on mathematical programming to find the best transistor sizes. Finally, we apply our proposed optimization formulation on True Single-Phase Clock (TSPC) flip-flops and show the simulation results.1 Keywords Static timing analysis, setup and hold times, NBTI, circuit re...

• Type: Conference
• Year: 2010
• Where: ISQED
• Authors: Hamed Abrishami, Safar Hatami, Massoud Pedram
• Keywords: Flip-flops, Hardware, Hold Times, ISQED 2010, Negative Bias Temperature Instability