1529 search results - page 112 / 306 » On Timing Analysis of Combinational Circuits |
ICCAD
2002
IEEE
14 years 5 months ago
2002
IEEE
The simulation of on-chip inductance using PEEC-based circuit analysis methods often requires the solution of a subproblem where an extracted inductance matrix must be multiplied ...
IJCNN
2007
IEEE
14 years 2 months ago
2007
IEEE
— Rapidly evolving businesses generate massive amounts of time-stamped data sequences and defy a demand for massively multivariate time series analysis. For such data the predict...
ICCAD
1998
IEEE
14 years 18 days ago
1998
IEEE
Abstract Althoughtremendousadvanceshave been accomplished in logic synthesis in the past two decades, in some cases logic synthesis still cannot attain the improvements possible by...
ECCV
2002
Springer
14 years 10 months ago
2002
Springer
We propose a method for constructing a video sequence of high space-time resolution by combining information from multiple lowresolution video sequences of the same dynamic scene. ...
DDECS
2007
IEEE
14 years 2 months ago
2007
IEEE
—An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with sp...