1529 search results - page 156 / 306 » On Timing Analysis of Combinational Circuits |
MICRO
2008
IEEE
14 years 2 months ago
2008
IEEE
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and dela...
ICCD
2008
IEEE
14 years 5 months ago
2008
IEEE
— Test-access mechanisms (TAMs) and test wrappers (e.g., the IEEE Standard 1500 wrapper) facilitate the modular testing of embedded cores in a core-based system-on-chip (SOC). Su...
MTDT
2003
IEEE
14 years 1 months ago
2003
IEEE
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
LICS
2012
IEEE
11 years 10 months ago
2012
IEEE
—We study the logic of dynamical systems, that is, logics and proof principles for properties of dynamical systems. Dynamical systems are mathematical models describing how the s...