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» On Timing Analysis of Combinational Circuits
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ISCAS
2006
IEEE
122views Hardware» more  ISCAS 2006»
14 years 2 months ago
256-channel integrated neural interface and spatio-temporal signal processor
Abstract- We present an architecture and VLSI implemen- Various strategies in the analysis of spatio-temporal dynamtation of a distributed neural interface and spatio-temporal ics ...
J. N. Y. Aziz, Roman Genov, B. R. Bardakjian, M. D...
VISSYM
2007
13 years 10 months ago
Relevance Driven Visualization of Financial Performance Measures
Visual data analysis has received a lot of research interest in recent years, and a wide variety of new visualization techniques and applications have been developed to improve in...
Hartmut Ziegler, Tilo Nietzschmann, Daniel A. Keim
SAC
2004
ACM
14 years 1 months ago
Axes-based visualizations with radial layouts
In the analysis of multidimensional data sets questions involving detection of extremal events, correlations, patterns and trends play an increasingly important role in a variety ...
Christian Tominski, James Abello, Heidrun Schumann
BROADNETS
2007
IEEE
14 years 3 days ago
Energy-efficient transmission for multimedia streams in last-hop wireless internet
Multimedia applications have unique characteristics that can be leveraged to design energy-efficient loss recovery mechanisms. Given their loss tolerance and strict timing requirem...
Albert F. Harris III, Robin Snader, Robin Kravets
ETS
2007
IEEE
128views Hardware» more  ETS 2007»
13 years 10 months ago
Selecting Power-Optimal SBST Routines for On-Line Processor Testing
Software-Based Self-Test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical embedded system applications. Among the mo...
Andreas Merentitis, Nektarios Kranitis, Antonis M....