1529 search results - page 200 / 306 » On Timing Analysis of Combinational Circuits |
KBSE
2000
IEEE
14 years 14 days ago
2000
IEEE
The majority of work carried out in the formal methods community throughout the last three decades has (for good reasons) been devoted to special languages designed to make it eas...
ICCD
2003
IEEE
14 years 5 months ago
2003
IEEE
With the circuit density available in today’s ASIC design systems, increased integration is possible creating more complexity in the design of a System on a Chip (SoC). IBM’s ...
SPAA
2004
ACM
14 years 1 months ago
2004
ACM
Given a general graph G, a fundamental problem is to find a spanning tree H that best approximates G by some measure. Often this measure is some combination of the congestion and...
GLOBECOM
2006
IEEE
14 years 2 months ago
2006
IEEE
— After identifying that current GMPLS specifications only allow for the implementation of a call blocking mode of operation that handles immediate-request calls (not book-ahead...
ICCAD
1999
IEEE
14 years 11 days ago
1999
IEEE
Available techniques for testing core-based systems-on-a-chip (SOCs) do not provide a systematic means for synthesising low-overhead test architectures and compact test solutions....