1529 search results - page 41 / 306 » On Timing Analysis of Combinational Circuits |
112
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ICCD
1995
IEEE
15 years 8 months ago
1995
IEEE
STARI is a high-speed signaling technique that uses both synchronous and self-timed circuits. To demonstrate STARI, a chip has been fabricated using the MOSIS 2 CMOS process. In a...
125
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MJ
2008
15 years 4 months ago
2008
This report is a brief review of the recent work on architectures for the prospective hybrid CMOS/nanowire/ nanodevice ("CMOL") circuits including digital memories, reco...
131
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DATE
2005
IEEE
15 years 10 months ago
2005
IEEE
A technique based on the sensitivity of the output to input waveform is presented for accurate propagation of delay information through a gate for the purpose of static timing ana...
113
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DAC
2002
ACM
16 years 5 months ago
2002
ACM
CT The traditional approach to worst-case static-timing analysis is becoming unacceptably conservative due to an ever-increasing number of circuit and process effects. We propose a...
117
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DATE
2005
IEEE
15 years 10 months ago
2005
IEEE
In this paper, we highlight a fast, effective and practical statistical approach that deals with inter and intra-die variations in VLSI chips. Our methodology is applied to a numb...