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» On Variations of Power Iteration
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ICCAD
2002
IEEE
103views Hardware» more  ICCAD 2002»
14 years 5 months ago
Synthesis of customized loop caches for core-based embedded systems
Embedded system programs tend to spend much time in small loops. Introducing a very small loop cache into the instruction memory hierarchy has thus been shown to substantially red...
Susan Cotterell, Frank Vahid
FPGA
2009
ACM
183views FPGA» more  FPGA 2009»
14 years 2 months ago
A comparison of via-programmable gate array logic cell circuits
Via-programmable gate arrays (VPGAs) offer a middle ground between application specific integrated circuits and field programmable gate arrays in terms of flexibility, manufac...
Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H...
ASPDAC
2009
ACM
102views Hardware» more  ASPDAC 2009»
14 years 2 months ago
Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction
Power delivery network (PDN) is a distributed RLC network with its dominant resonance frequency in the low-to-middle frequency range. Though high-performance chips’ working freq...
Yiyu Shi, Jinjun Xiong, Howard Chen, Lei He
DSD
2008
IEEE
187views Hardware» more  DSD 2008»
14 years 2 months ago
How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design
Ultra low power digital systems are key for any future wireless sensor nodes but also inside nomadic embedded systems (such as inside the digital front end of software defined rad...
Giacomo Paci, A. Nackaerts, Francky Catthoor, Luca...
DSD
2008
IEEE
145views Hardware» more  DSD 2008»
14 years 2 months ago
Formulating MITF for a Multicore Processor with SEU Tolerance
While shrinking geometries of embedded LSI devices is beneficial for portable intelligent systems, it is increasingly susceptible to influences from electrical noise, process vari...
Toshimasa Funaki, Toshinori Sato