1444 search results - page 71 / 289 » On Variations of Power Iteration |
DATE
2008
IEEE
14 years 4 months ago
2008
IEEE
Abstract—Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testi...
DATE
2005
IEEE
14 years 4 months ago
2005
IEEE
— This paper suggests a methodology to decrease the power of a static CMOS standard cell design at layout level by focusing on switched capacitance. The term switched is the key:...
DATE
2004
IEEE
14 years 2 months ago
2004
IEEE
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
TCOM
2010
13 years 8 months ago
2010
Multiple subcarrier modulation is an appealing scheme for high-data rate optical communication. However a major drawback is its low average power efficiency. While subcarrier res...
TSP
2010
13 years 5 months ago
2010
Abstract--In this paper, the problem of estimating direction-ofarrival (DOA) of multiple uncorrelated sources from single antenna power measurements is addressed. Utilizing the fac...