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» On a Resequencing Model for High Speed Networks
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DATE
2002
IEEE
95views Hardware» more  DATE 2002»
14 years 10 days ago
Optimal Transistor Tapering for High-Speed CMOS Circuits
Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in highperformance circuit design with a view to minimizing the delay of a FE...
Li Ding 0002, Pinaki Mazumder
ICC
2007
IEEE
137views Communications» more  ICC 2007»
14 years 1 months ago
A Novel Algorithm and Architecture for High Speed Pattern Matching in Resource-Limited Silicon Solution
— Network Intrusion Detection Systems (NIDS) are more and more important for identifying and preventing the malicious attacks over the network. This paper proposes a novel cost-e...
Nen-Fu Huang, Yen-Ming Chu, Chi-Hung Tsai, Chen-Yi...
GECCO
2008
Springer
363views Optimization» more  GECCO 2008»
13 years 8 months ago
Towards high speed multiobjective evolutionary optimizers
One of the major difficulties when applying Multiobjective Evolutionary Algorithms (MOEA) to real world problems is the large number of objective function evaluations. Approximate...
A. K. M. Khaled Ahsan Talukder
RECONFIG
2008
IEEE
225views VLSI» more  RECONFIG 2008»
14 years 1 months ago
A Hardware Filesystem Implementation for High-Speed Secondary Storage
Platform FPGAs are capable of hosting entire Linuxbased systems including standard peripherals, integrated network interface cards and even disk controllers on a single chip. File...
Ashwin A. Mendon, Ron Sass
ACISP
2000
Springer
13 years 11 months ago
High Performance Agile Crypto Modules
This paper examines the impact of the primary symmetric key cryptographic operation on network data streams, encryption of user data, have on the overall tra c throughput. The encr...
Chandana Gamage, Jussipekka Leiwo, Yuliang Zheng