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» On computational limitations of neural network architectures
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MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 6 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt
VLSID
2004
IEEE
170views VLSI» more  VLSID 2004»
14 years 9 months ago
On-chip networks: A scalable, communication-centric embedded system design paradigm
As chip complexity grows, design productivity boost is expected from reuse of large parts and blocks of previous designs with the design effort largely invested into the new parts...
Jörg Henkel, Srimat T. Chakradhar, Wayne Wolf
TC
2010
13 years 3 months ago
Model-Driven System Capacity Planning under Workload Burstiness
In this paper, we define and study a new class of capacity planning models called MAP queueing networks. MAP queueing networks provide the first analytical methodology to describe ...
Giuliano Casale, Ningfang Mi, Evgenia Smirni
IPPS
2007
IEEE
14 years 3 months ago
A Peer-to-Peer Infrastructure for Autonomous Grid Monitoring
Modern grids have become very complex by their size and their heterogeneity. It makes the deployment and maintenance of systems a difficult task requiring lots of efforts from ad...
Laurent Baduel, Satoshi Matsuoka
NOSSDAV
2011
Springer
12 years 11 months ago
A measurement study of resource utilization in internet mobile streaming
The pervasive usage of mobile devices and wireless networking support have enabled more and more Internet streaming services to all kinds of heterogeneous mobile devices. However,...
Yao Liu, Fei Li, Lei Guo, Songqing Chen