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IPPS
2006
IEEE
14 years 1 months ago
An optimal architecture for a DDC
Digital Down Conversion (DDC) is an algorithm, used to lower the amount of samples per second by selecting a limited frequency band out of a stream of samples. A possible DDC algo...
Tjerk Bijlsma, Pascal T. Wolkotte, Gerard J. M. Sm...
TRIDENTCOM
2006
IEEE
14 years 1 months ago
Light-trail testbed for metro optical networks
— Telecommunication networks have rapidly added staggering amounts of capacity to their long haul networks at low costs per bit using DWDM technologies. Concurrently, there has b...
Nathan A. VanderHorn, Srivatsan Balasubramanian, M...
DATE
2005
IEEE
118views Hardware» more  DATE 2005»
14 years 1 months ago
An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms
In this work we consider battery powered portable systems which either have Field Programmable Gate Arrays (FPGA) or voltage and frequency scalable processors as their main proces...
Jawad Khan, Ranga Vemuri
ANCS
2005
ACM
14 years 1 months ago
A novel reconfigurable hardware architecture for IP address lookup
IP address lookup is one of the most challenging problems of Internet routers. In this paper, an IP lookup rate of 263 Mlps (Million lookups per second) is achieved using a novel ...
Hamid Fadishei, Morteza Saheb Zamani, Masoud Sabae...
FPGA
2001
ACM
139views FPGA» more  FPGA 2001»
14 years 6 days ago
A memory coherence technique for online transient error recovery of FPGA configurations
The partial reconfiguration feature of some of the currentgeneration Field Programmable Gate Arrays (FPGAs) can improve dependability by detecting and correcting errors in onchip ...
Wei-Je Huang, Edward J. McCluskey