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» On load latency in low-power caches
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IPPS
2007
IEEE
14 years 1 months ago
Load Miss Prediction - Exploiting Power Performance Trade-offs
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
Konrad Malkowski, Greg M. Link, Padma Raghavan, Ma...
NOCS
2009
IEEE
14 years 2 months ago
Best of both worlds: A bus enhanced NoC (BENoC)
While NoCs are efficient in delivering high throughput point-to-point traffic, their multi-hop operation is too slow for latency sensitive signals. In addition, NoCS are inefficie...
Ran Manevich, Isask'har Walter, Israel Cidon, Avin...
FPL
2007
Springer
136views Hardware» more  FPL 2007»
14 years 1 months ago
A Load/Store Unit for a Memcpy Hardware Accelerator
Recently, a dedicated hardware accelerator was proposed that works in conjunction with caches found next to modern-day microprocessors, to speedup the commonly utilized memcpy ope...
Stamatis Vassiliadis, Filipa Duarte, Stephan Wong
IPPS
2000
IEEE
13 years 11 months ago
Reducing Ownership Overhead for Load-Store Sequences in Cache-Coherent Multiprocessors
Parallel programs that modify shared data in a cachecoherent multiprocessor with a write-invalidate coherence protocol create ownership overhead in the form of ownership acquisiti...
Jim Nilsson, Fredrik Dahlgren
ASIAMS
2008
IEEE
14 years 1 months ago
Intelligent Web Caching Using Neurocomputing and Particle Swarm Optimization Algorithm
Web caching is a technology for improving network traffic on the internet. It is a temporary storage of Web objects (such as HTML documents) for later retrieval. There are three s...
Sarina Sulaiman, Siti Mariyam Hj. Shamsuddin, Fadn...