305 search results - page 11 / 61 » On modeling top-down VLSI design |
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper describes a SPICE model development methodology for Quantum-Dot Cellular Automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simula...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient ...
GLVLSI
1998
IEEE
13 years 12 months ago
1998
IEEE
Important layout properties of electronic designs include interconnection length values, clock speed, area requirements, and power dissipation. A reliable estimation of those prop...
VLSI
2010
Springer
13 years 2 months ago
2010
Springer
Although local biasing of components used in an analog circuit is shown to be a very attractive design methodology, significantly simplifying the design procedure [3], it makes the...
GLVLSI
2009
IEEE
13 years 11 months ago
2009
IEEE
Design debug remains one of the major bottlenecks in the VLSI design cycle today. Existing automated solutions strive to aid engineers in reducing the debug effort by identifying ...