305 search results - page 16 / 61 » On modeling top-down VLSI design |
ISVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
Mesh interconnect can be efficiently utilized while tree networks encourage the short routing distances. In this paper, we present the property analysis of a cluster-based interc...
CODES
2008
IEEE
13 years 7 months ago
2008
IEEE
With power becoming a major constraint for multi-processor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is cr...
DATE
1999
IEEE
13 years 12 months ago
1999
IEEE
Power estimation is important for system-level exploration and trade-off analysis of VLSI systems. A power estimator for high-speed analog to digital converters that exploits info...
FCCM
1998
IEEE
13 years 12 months ago
1998
IEEE
ended abstract defines a class of architectures for pipeline reconfigurable FPGAs by parameterizing a generic model. This class of architectures is sufficiently general to allow e...
ARVLSI
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper presents a new architecture style for the design of a parallel floating point multiplier. The proposed architecture is a synergy of trees and arrays. Architectural mod...