305 search results - page 20 / 61 » On modeling top-down VLSI design |
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Models of simulation program with integrated circuit emphasis (SPICE) are currently playing a central role in the connection between circuit design and chip fabrication communitie...
GLVLSI
2003
IEEE
14 years 26 days ago
2003
IEEE
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
GLVLSI
2003
IEEE
14 years 26 days ago
2003
IEEE
—Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effectiv...
GLVLSI
1999
IEEE
13 years 12 months ago
1999
IEEE
The Elmore delay is the metric of choice for performancedriven design applications due to its simple, explicit form and ease with which sensitivity information can be calculated. ...
ITC
1998
IEEE
13 years 11 months ago
1998
IEEE
Previously-proposed strategies for VLSI fault diagnosis have su ered from a variety of self-imposed limitations. Some techniques are limited to a speci c fault model, and many wil...