305 search results - page 26 / 61 » On modeling top-down VLSI design |
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
The development of application specific instruction set processors comprises several design phases: architecture exploration, software tools design, system verification and design...
DFT
2003
IEEE
14 years 25 days ago
2003
IEEE
This paper proposes a new fault model and its modeling and analysis methods in a clockless asynchronous wave pipeline for extensive yield evaluation and assurance. It is highly de...
VTS
2002
IEEE
14 years 13 days ago
2002
IEEE
A device testing method called Transient Signal Analysis (TSA) is subjected to elements of a real process and testing environment in this paper. Simulations experiments are design...
ISVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
Formal verification has become an important step in circuit and system design. A prominent technique is Bounded Model Checking (BMC) which is widely used in industry. In BMC it i...
ISVLSI
2003
IEEE
14 years 25 days ago
2003
IEEE
The need for small, high speed, low power computers as the end of Moore’s law approaches is driving research into nanotechnology. These novel devices have significantly differe...