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» On modeling top-down VLSI design
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SAMOS
2005
Springer
14 years 1 months ago
Automatic FIR Filter Generation for FPGAs
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. P...
Holger Ruckdeschel, Hritam Dutta, Frank Hannig, J&...
GLVLSI
2006
IEEE
144views VLSI» more  GLVLSI 2006»
14 years 1 months ago
Crosstalk analysis in nanometer technologies
Process variations have become a key concern of circuit designers because of their significant, yet hard to predict impact on performance and signal integrity of VLSI circuits. St...
Shahin Nazarian, Ali Iranli, Massoud Pedram
ISSS
2002
IEEE
141views Hardware» more  ISSS 2002»
14 years 13 days ago
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and r...
Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin
GLVLSI
2010
IEEE
209views VLSI» more  GLVLSI 2010»
14 years 18 days ago
Enhancing debugging of multiple missing control errors in reversible logic
Researchers are looking for alternatives to overcome the upcoming limits of conventional hardware technologies. Reversible logic thereby established itself as a promising directio...
Jean Christoph Jung, Stefan Frehse, Robert Wille, ...
VLSID
2010
IEEE
155views VLSI» more  VLSID 2010»
13 years 5 months ago
Synchronized Generation of Directed Tests Using Satisfiability Solving
Directed test generation is important for the functional verification of complex system-on-chip designs. SAT based bounded model checking is promising for counterexample generatio...
Xiaoke Qin, Mingsong Chen, Prabhat Mishra