305 search results - page 34 / 61 » On modeling top-down VLSI design |
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
Boolean Satisfiability (SAT) solvers are popular engines used throughout the verification world. Bounded sequential problems such as bounded model checking and bounded sequentia...
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
The inductance effects become significant for sub-100nm process designs due to increasing interconnect lengths, lower interconnect resistance values and fast signal transition tim...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
Predictive delay analysis is presented for a representative CMOS inverter with submicron device size using PREDICTMOS MOSFET model. As against SPICE, which adopts a time consuming...
ISPD
2003
ACM
14 years 23 days ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
GLVLSI
2008
IEEE
14 years 1 months ago
2008
IEEE
In this paper, we propose a novel statistical capacitance extraction method for interconnects considering process variations. The new method, called statCap, is based on the spect...