305 search results - page 44 / 61 » On modeling top-down VLSI design |
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
We perform a detailed study of various crosstalk scenarios in VDSM technologies by using a distributed model of the crosstalk site and make a number of key observations about the ...
DAC
2006
ACM
14 years 1 months ago
2006
ACM
VLSI engineers have traditionally used a variety of CAD analysis tools (e.g. SPICE) to deal with variability. As we go into deep sub micron issues, the analysis is becoming harder...
ACSD
2005
IEEE
14 years 1 months ago
2005
IEEE
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
DAC
2011
ACM
12 years 7 months ago
2011
ACM
In the era of deep sub-wavelength lithography for nanometer VLSI designs, manufacturability and yield issues are critical and need to be addressed during the key physical design i...
FCCM
2011
IEEE
12 years 11 months ago
2011
IEEE
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...