Sciweavers

305 search results - page 45 / 61
» On modeling top-down VLSI design
Sort
View
ISPD
2003
ACM
105views Hardware» more  ISPD 2003»
14 years 22 days ago
Partition-driven standard cell thermal placement
The thermal problem has been emerged as one of the key issues for next-generation IC design. In this paper, we propose a scheme to achieve better thermal distribution for partitio...
Guoqiang Chen, Sachin S. Sapatnekar
VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
14 years 7 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...
DAC
2003
ACM
14 years 8 months ago
Efficient model order reduction including skin effect
Skin effect makes interconnect resistance and inductance frequency dependent. This paper addresses the problem of efficiently estimating the signal characteristics of any RLC netw...
Shizhong Mei, Chirayu S. Amin, Yehea I. Ismail
VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
14 years 7 months ago
Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
Banit Agrawal, Timothy Sherwood, Chulho Shin, Simo...
ISLPED
2005
ACM
108views Hardware» more  ISLPED 2005»
14 years 1 months ago
Replacing global wires with an on-chip network: a power analysis
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
Seongmoo Heo, Krste Asanovic