305 search results - page 47 / 61 » On modeling top-down VLSI design |
FCCM
2008
IEEE
14 years 1 months ago
2008
IEEE
The map-reduce model requires users to express their problem in terms of a map function that processes single records in a stream, and a reduce function that merges all mapped out...
RECONFIG
2009
IEEE
14 years 2 months ago
2009
IEEE
BLASTn is a ubiquitous tool used for large scale DNA analysis. Detailed profiling tests reveal that the most computationally intensive sections of the BLASTn algorithm are the sc...
ISVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
Contemporary SoC design involves the proper selection of cores from a reference platform. Such selection implies the design exploration of alternative CPUs, which requires the gen...
FCCM
2006
IEEE
14 years 1 months ago
2006
IEEE
Recently, platform FPGAs that integrate sequential processors with a spatial fabric have become prevalent. While these hybrid architectures ease the burden of integrating sequenti...
ANSS
2001
IEEE
13 years 11 months ago
2001
IEEE
In this work, we study the different buffering techniques used in the literature to solve the contention problem in A TM switching architectures. The objective of our study is to ...