305 search results - page 56 / 61 » On modeling top-down VLSI design |
ISCAS
2011
IEEE
12 years 11 months ago
2011
IEEE
— we present an implementation of a programmable axonal propagation delay circuit which uses one first-order logdomain low-pass filter. Delays may be programmed in the 550ms rang...
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
DAC
1998
ACM
14 years 8 months ago
1998
ACM
In this paper we present a statistical method for estimating the maximum power consumption in VLSI circuits. The method is based on the theory of extreme order statistics applied ...
VLSID
2003
IEEE
14 years 7 months ago
2003
IEEE
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
ISVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
In sub-90nm technologies, more frequent hard faults pose a serious burden on processor design and yield control. In addition to manufacturing-time chip repair schemes, microarchit...