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» On modeling top-down VLSI design
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ASPDAC
1999
ACM
168views Hardware» more  ASPDAC 1999»
13 years 12 months ago
An Integrated Battery-Hardware Model for Portable Electronics
- We describe an integrated model of the hardware and the battery sub-systems in batterypowered VLSI systems. We demonstrate that, under this model and for a fixed operating voltag...
Massoud Pedram, Chi-Ying Tsui, Qing Wu
VLSI
2012
Springer
12 years 3 months ago
A Signature-Based Power Model for MPSoC on FPGA
e technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set sim...
Roberta Piscitelli, Andy D. Pimentel
ISCAS
2003
IEEE
153views Hardware» more  ISCAS 2003»
14 years 27 days ago
A VLSI model of range-tuned neurons in the bat echolocation system
The neural computations that support bat echolocation are of great interest to both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the ...
Matthew Cheely, Timothy K. Horiuchi
ISQED
2008
IEEE
101views Hardware» more  ISQED 2008»
14 years 2 months ago
Projection-Based Piecewise-Linear Response Surface Modeling for Strongly Nonlinear VLSI Performance Variations
Large-scale process fluctuations (particularly random device mismatches) at nanoscale technologies bring about highdimensional strongly nonlinear performance variations that canno...
Xin Li, Yu Cao
RSP
2003
IEEE
149views Control Systems» more  RSP 2003»
14 years 27 days ago
Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA
In this paper, an efficient design flow integrating Mentor Graphics Precesion C and HDL designer is derived. In this hybrid prototyping environment, efficient FPGA architectures a...
Yuanbin Guo, Gang Xu, Dennis McCain, Joseph R. Cav...