315 search results - page 14 / 63 » On reducing load store latencies of cache accesses |
WMPI
2004
ACM
14 years 1 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
One of the major issues faced by the semiconductor industry today is that of reducing chip yields. As the process technologies have scaled to smaller feature sizes, chip yields ha...
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
As processor speeds increase and memory latency becomes more critical, intelligent design and management of secondary caches becomes increasingly important. The efficiency of curr...
CNSR
2005
IEEE
14 years 1 months ago
2005
IEEE
Web caching has been recognized as an effective scheme to alleviate the service bottleneck and reduce the network traffic, thereby minimizing the user access latency on the Intern...
ISCA
1994
IEEE
13 years 11 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...