315 search results - page 27 / 63 » On reducing load store latencies of cache accesses |
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
Content Addressable Memories (CAM) are widely used for the tag portions in highly associative caches. Since data are not explicitly read out of tag array in CAM search, the detect...
DATE
2003
IEEE
14 years 28 days ago
2003
IEEE
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
PATMOS
2010
Springer
13 years 5 months ago
2010
Springer
In most modern processor designs the L1 data cache has become a major consumer of power due to its increasing size and high frequency access rate. In order to reduce this power con...
ASPLOS
1991
ACM
13 years 11 months ago
1991
ACM
Blocking is a well-known optimization technique for improving the effectiveness of memory hierarchies. Instead of operating on entire rows or columns of an array, blocked algorith...
HPCA
2004
IEEE
14 years 8 months ago
2004
IEEE
Data communications between producer instructions and consumer instructions through memory incur extra delays that degrade processor performance. In this paper, we introduce a new...