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» On reducing load store latencies of cache accesses
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LCTRTS
2007
Springer
14 years 1 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
FAST
2003
13 years 9 months ago
Data Staging on Untrusted Surrogates
We show how untrusted computers can be used to facilitate secure mobile data access. We discuss a novel architecture, data staging, that improves the performance of distributed ï¬...
Jason Flinn, Shafeeq Sinnamohideen, Niraj Tolia, M...
SRDS
2007
IEEE
14 years 1 months ago
Enhancing Edge Computing with Database Replication
As the use of the Internet continues to grow explosively, edge computing has emerged as an important technique for delivering Web content over the Internet. Edge computing moves d...
Yi Lin, Bettina Kemme, Marta Patiño-Mart&ia...
DATE
2003
IEEE
141views Hardware» more  DATE 2003»
14 years 27 days ago
On-chip Stack Based Memory Organization for Low Power Embedded Architectures
This paper presents a on-chip stack based memory organization that effectively reduces the energy dissipation in programmable embedded system architectures. Most embedded systems ...
Mahesh Mamidipaka, Nikil D. Dutt
IEEEPACT
2000
IEEE
13 years 12 months ago
On Some Implementation Issues for Value Prediction on Wide-Issue ILP Processors
In this paper, we look at two issues which could affect the performance of value prediction on wide-issue ILP processors. One is the large number of accesses to the value predicti...
Sang Jeong Lee, Pen-Chung Yew