315 search results - page 4 / 63 » On reducing load store latencies of cache accesses |
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
The load-store unit is a performance critical component of a dynamically-scheduled processor. It is also a complex and non-scalable component. Several recently proposed techniques...
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
ICS
2005
Tsinghua U.
14 years 1 months ago
2005
Tsinghua U.
With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors. However, with reducing feature si...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
Increasing cache latencies limit L1 cache sizes. In this paper we investigate restrictive compression techniques for level 1 data cache, to avoid an increase in the cache access l...
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...