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» On software design for stochastic processors
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MM
2009
ACM
217views Multimedia» more  MM 2009»
14 years 2 months ago
Streaming HD H.264 encoder on programmable processors
Programmable processors have great advantage over dedicated ASIC design under intense time-to-market pressure. However, realtime encoding of high-definition (HD) H.264 video (up t...
Nan Wu, Mei Wen, Wei Wu, Ju Ren, Huayou Su, Changq...
GLVLSI
1998
IEEE
122views VLSI» more  GLVLSI 1998»
13 years 12 months ago
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
Luca Benini, Giovanni De Micheli, Alberto Macii, E...
ISLPED
2009
ACM
168views Hardware» more  ISLPED 2009»
14 years 2 months ago
A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management
An energy efficient object recognition processor is proposed for real-time visual applications. Its energy efficiency is improved by lowering average power consumption while susta...
Joo-Young Kim, Seungjin Lee, Jinwook Oh, Minsu Kim...
MICRO
2003
IEEE
106views Hardware» more  MICRO 2003»
14 years 1 months ago
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cor...
Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, P...
VLSID
2001
IEEE
144views VLSI» more  VLSID 2001»
14 years 8 months ago
Next Generation Network Processors
Networking hardware manufacturers face the dual demands of supporting ever increasing bandwidth requirements, while also delivering new features, such as the ability to implement ...
Deepak Kataria