166 search results - page 14 / 34 » On testing delay faults in macro-based combinational circuit... |
CEC
2005
IEEE
14 years 1 months ago
2005
IEEE
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...
ATS
2003
IEEE
14 years 1 months ago
2003
IEEE
Capacitive crosstalk can give rise to slowdown of signals that can propagate to a circuit output and create a functional error. A test generation methodology, called XGEN, was dev...
ET
2010
13 years 6 months ago
2010
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
CORR
2010
Springer
13 years 7 months ago
2010
Springer
In this paper a new solution is proposed for testing simple stwo stage electronic circuits. It minimizes the number of tests to be performed to determine the genuinity of the circ...
ITC
2003
IEEE
14 years 1 months ago
2003
IEEE
: The paper presents a novel technique for generating effective vectors for delay defects. The test set achieves high path delay fault coverage to capture smalldistributed delay de...