166 search results - page 15 / 34 » On testing delay faults in macro-based combinational circuit... |
ATS
2000
IEEE
14 years 6 days ago
2000
IEEE
Because domino logic design offers smaller area and faster delay than conventional CMOS design, it is very popular in the high-performance processor design. However, domino logic ...
TCAD
2002
13 years 7 months ago
2002
A test pattern generator (TPG) for built-in self-test (BIST), which can reduce switching activity during test application, is proposed. The proposed TPG, called dual-speed LFSR (DS...
ITC
1993
IEEE
13 years 12 months ago
1993
IEEE
ÐPseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones. The testing ensures detection of all detecta...
VTS
2003
IEEE
14 years 1 months ago
2003
IEEE
Irreversible computation necessarily results in energy dissipation due to information loss. While small in comparison to the power consumption of today’s VLSI circuits, if curre...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
－ We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and cr...