166 search results - page 31 / 34 » On testing delay faults in macro-based combinational circuit... |
TC
1998
13 years 7 months ago
1998
ion Techniques for Validation Coverage Analysis and Test Generation Dinos Moundanos, Jacob A. Abraham, Fellow, IEEE, and Yatin V. Hoskote —The enormous state spaces which must be...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— The rapid control of sonar-guided vehicles through obstacle fields has been a goal of robotics for decades. How sensory data is represented strongly affects how obstacles and g...
TVLSI
2002
13 years 7 months ago
2002
Circular built-in self-test (BIST) is a "test per clock" scheme that offers many advantages compared with conventional BIST approaches in terms of low area overhead, simp...
FDTC
2006
Springer
13 years 11 months ago
2006
Springer
Abstract. Balanced gates are an effective countermeasure against power analysis attacks only if they can be guaranteed to maintain their power balance. Traditional testing and reli...
VTS
2006
IEEE
14 years 1 months ago
2006
IEEE
We tackle the problem of fault-free assumptions in current PLB and interconnect built-in-self-test (BIST) techniques for FPGAs. These assumptions were made in order to develop stro...