166 search results - page 32 / 34 » On testing delay faults in macro-based combinational circuit... |
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
— Reduction in test power is important to improve battery life in portable devices employing periodic self-test, to increase reliability of testing and to reduce test-cost. In sc...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
The lack of good "correlation" between pre-silicon simulated delays and measured delays on silicon (silicon data) has spurred efforts on so-called silicon debug. The ide...
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
In modern SoCs, embedded memories occupy the largest part of the chip area and include an even larger amount of active devices. As memories are designed very tightly to the limits...
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
The high unit cost of FPGA devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of FPGA devices, resulting in the developmen...
CONSTRAINTS
2007
13 years 7 months ago
2007
In the ECAD area, the Test Generation (TG) problem consists in finding an input vector test for some possible diagnosis (a set of faults) of a digital circuit. Such tests may have ...