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DAC
2004
ACM
13 years 11 months ago
On test generation for transition faults with minimized peak power dissipation
This paper presents a method of generating tests for transition faults using tests for stuck-at faults such that the peak power is the minimum possible using a given set of tests ...
Wei Li, Sudhakar M. Reddy, Irith Pomeranz
ENGL
2007
180views more  ENGL 2007»
13 years 7 months ago
Reordering Algorithm for Minimizing Test Power in VLSI Circuits
— Power consumption has become a crucial concern in Built In Self Test (BIST) due to the switching activity in the circuit under test(CUT). In this paper we present a novel metho...
K. Paramasivam, K. Gunavathi
ICCAD
1998
IEEE
96views Hardware» more  ICCAD 1998»
13 years 12 months ago
Test set compaction algorithms for combinational circuits
This paper presents two new algorithms, Redundant Vector Elimination(RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under th...
Ilker Hamzaoglu, Janak H. Patel
ICST
2008
IEEE
14 years 2 months ago
Efficient Test Data Generation for Variables with Complex Dependencies
This paper introduces a new method for generating test data that combines the benefits of equivalence partitioning, boundary value analysis and cause-effect analysis. It is suitab...
Armin Beer, Stefan Mohacsi
IPPS
1998
IEEE
13 years 12 months ago
Self-Testing Fault-Tolerant Real-Time Systems
We propose a periodic diagnostic algorithm based on the testing model of computation for real-time systems. The diagnostic task runs on every processor of the system. When the task...
M. Rooholamini, Seyed H. Hosseini