418 search results - page 6 / 84 » On the Adders with Minimum Tests |
ITC
1993
IEEE
13 years 11 months ago
1993
IEEE
ÐPseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones. The testing ensures detection of all detecta...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
A concurrent core test approach is proposed to reduce the test cost of SOC. Multiple cores in SOC can be tested simultaneously by using a shared test set and scan chain disable. P...
GLVLSI
2003
IEEE
14 years 29 days ago
2003
IEEE
The current trends in high performance integrated circuits are towards faster and more powerful circuits in the giga-hertz range and even further. As the more complex Integrated C...
ISQED
2002
IEEE
14 years 17 days ago
2002
IEEE
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
AMC
2006
13 years 7 months ago
2006
In this paper, given a balance scale and the information that there are exactly two different defective coins present, the authors consider the problem of ascertaining the minimum...