In this paper we present an algorithm for automatic extraction of system behavior from a structural Verilog specification. The algorithm generates a series-parallel poset expressi...
We describe the design and the present state of the verification tool Augur 2 which is currently being developed. It is based on Augur 1, a tool which can analyze graph transforma...
We describe two things. First, we present a uniform framework for object oriented specification and verification of hardware. For this purpose the object oriented language `e'...
Tommy Kuhn, Tobias Oppold, Markus Winterholer, Wol...
In this paper, we present our Advanced TCP Evaluation Testbed on Mixed Wired Internet and Satellite Environments. Categories and Subject Descriptors C.2.2 [Network Protocols]:–A...
Rosario Firrincieli, Carlo Caini, Cesar Marcondes,...