Sciweavers

2607 search results - page 18 / 522
» On the Architecture of System Verification Environments
Sort
View
DAC
1996
ACM
13 years 11 months ago
RTL Emulation: The Next Leap in System Verification
ion. Production use of text-based methodology has enabled designers to capture designs of hundreds of thousands of gates using graphic ESDA tools. Source: Data Quest (Verilog/VHDL ...
Sanjay Sawant, Paul Giordano
EURODAC
1995
IEEE
180views VHDL» more  EURODAC 1995»
13 years 11 months ago
Integration of VHDL into a system design environment
Verification of image processing systems is mainly done on the basis of image sequence simulations. To achieve high simulation efficiency, our compiled code simulator MSIPC offers...
Ludwig Schwoerer, Matthias Lück, Hartmut Schr...
SIGSOFT
2009
ACM
14 years 8 months ago
Probabilistic environments in the quantitative analysis of (non-probabilistic) behaviour models
System specifications have long been expressed through automata-based languages, enabling verification techniques such as model checking. These verification techniques can assess ...
Esteban Pavese, Sebastián Uchitel, Ví...
DAC
2002
ACM
14 years 8 months ago
Schedulability of event-driven code blocks in real-time embedded systems
Many real-time embedded systems involve a collection of independently executing event-driven code blocks, having hard real-time constraints. Tasks in many such systems, like netwo...
Samarjit Chakraborty, Thomas Erlebach, Simon K&uum...
DAC
2009
ACM
13 years 11 months ago
Fast vectorless power grid verification using an approximate inverse technique
Power grid verification in modern integrated circuits is an integral part of early system design where adjustments can be most easily incorporated. In this work, we describe an ea...
Nahi H. Abdul Ghani, Farid N. Najm