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» On the Circuit Implementation Problem
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ICDE
2010
IEEE
248views Database» more  ICDE 2010»
14 years 7 months ago
FPGA Acceleration for the Frequent Item Problem
Abstract-- Field-programmable gate arrays (FPGAs) can provide performance advantages with a lower resource consumption (e.g., energy) than conventional CPUs. In this paper, we show...
Gustavo Alonso, Jens Teubner, René Mül...
IOLTS
2007
IEEE
124views Hardware» more  IOLTS 2007»
14 years 1 months ago
On-Line Self-Healing of Circuits Implemented on Reconfigurable FPGAs
i To boost logic density and reduce per unit power consumption SRAM-based FPGAs manufacturers adopted nanometric technologies. However, this technology is highly vulnerable to radi...
Manuel G. Gericota, Luís F. Lemos, Gustavo ...
FPGA
2005
ACM
90views FPGA» more  FPGA 2005»
14 years 29 days ago
Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits
Abstract—As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are increasingly being used to implement large arithmetic-intensive applications, which ...
Andy Gean Ye, Jonathan Rose
IEEECIT
2006
IEEE
14 years 1 months ago
ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation
In this paper, we propose a new scheduling method for asynchronous circuits in bundled-data implementation. The method is based on integer linear programming (ILP) which explores ...
Hiroshi Saito, Nattha Jindapetch, Tomohiro Yoneda,...
ICONIP
2007
13 years 8 months ago
Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning
We proposed a neural segmentation model that is suitable for implementation in analog VLSIs using conventional CMOS technology. The model consists of neural oscillators mutually co...
Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asa...