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» On the Complexity of Circuit Satisfiability
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156
Voted
VTS
2007
IEEE
135views Hardware» more  VTS 2007»
16 years 10 days ago
High Level Synthesis of Degradable ASICs Using Virtual Binding
—As the complexity of the integrated circuits increases, they become more susceptible to manufacturing faults, decreasing the total process yield. Thus, it would be desirable to ...
Nima Honarmand, A. Shahabi, Hasan Sohofi, Maghsoud...
149
Voted
ACSD
2005
IEEE
144views Hardware» more  ACSD 2005»
15 years 11 months ago
An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
Alexander B. Smirnov, Alexander Taubin, Ming Su, M...
ISPD
2004
ACM
161views Hardware» more  ISPD 2004»
15 years 11 months ago
Early-stage power grid analysis for uncertain working modes
High performance integrated circuits are now reaching the 100-plus watt regime, and power delivery and power grid signal integrity have become critical. Analyzing the performance ...
Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
ICCAD
2003
IEEE
205views Hardware» more  ICCAD 2003»
15 years 11 months ago
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
Aseem Agarwal, David Blaauw, Vladimir Zolotov
ITC
2003
IEEE
197views Hardware» more  ITC 2003»
15 years 11 months ago
Critical Timing Analysis in Microprocessors Using Near-IR Laser Assisted Device Alteration (LADA)
A scalable laser-based timing analysis technique we call laser assisted device alteration (LADA) is introduced for the rapid isolation and analysis of defect-free performance limi...
Jeremy A. Rowlette, Travis M. Eiles